The statements in this section merely provide background information related to the present disclosure and do not constitute prior art.
A semiconductor memory device includes a memory cell array for storing data, peripheral circuits configured to program data in the memory cell array, or read or erase the programmed data, and a control circuit configured to control the peripheral circuits.
The memory cell array includes a plurality of memory blocks, and each of the plurality of memory blocks includes a plurality of memory cells. Memory cells are classified as a single-level cells (SLCs) having one program state per cell, and mufti-level cells (MLCs) having various program states per cell. MLCs are being used more recently. However, the inventor(s) has noted that since MLCs have a narrow width of each threshold voltage distribution, retention characteristics are design considerations. Examples of lowering the retention characteristics will be explained below.
FIG. 1A is a diagram of explaining a threshold voltage change of memory cells in an erase state.
Referring to FIG. 1A, a threshold voltage ER1 of memory cells in an erase state increases to a threshold voltage ER2 due to a read or program disturbance when a read or program operation is performed. The inventor(s) has experienced that, particularly, when the threshold voltage ER2 is higher than a read voltage (or verifying voltage), it is difficult to differentiate the erase state and the program state.
FIG. 1B is a diagram of explaining a threshold voltage change of memory cells in a program state.
Referring to FIG. 1B, a threshold voltage PGM1 of memory cells in a program state decreases to a threshold voltage PGM2 as time passes. This phenomenon occurs while electrons trapped in one memory cell escape. In particular, since the MLC in which one memory cell can be programmed in various states has a narrow width of each threshold voltage distribution and short intervals between different threshold voltage distributions, a read voltage (or verifying voltage) is included in the changed threshold voltage PGM2 distribution.
As described above, the inventor(s) has experienced that when the retention characteristics of memory cells in the erase state or the program state deteriorate, reliability of the read operation and the erase operation is lowered. Accordingly, the inventor(s) has experienced that reliability of the semiconductor memory device for performing the program operation, the read operation, and the erase operation is also lowered.